IEEE Transactions on Computers
A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
A threshold of ln n for approximating set cover
Journal of the ACM (JACM)
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Approximation algorithms
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
A Factor 2 Approximation Algorithm for the Generalized Steiner Network Problem
FOCS '98 Proceedings of the 39th Annual Symposium on Foundations of Computer Science
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Waveform Independent Gate Model for Accurate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Practical techniques to reduce skew and its variations in buffered clock networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Proceedings of the 2011 international symposium on Physical design
SWAT: simulator for waveform-accurate timing including parameter variations and transistor aging
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
Proceedings of the International Conference on Computer-Aided Design
Clock mesh synthesis with gated local trees and activity driven register clustering
Proceedings of the International Conference on Computer-Aided Design
Multi-corner multi-voltage domain clock mesh design
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Clock mesh has been widely used to distribute the clock signal across the chip. Clock mesh is driven by a top-level tree and a set of mesh buffers. We present fast and efficient combinatorial algorithms to simultaneously identify the candidate locations as well as sizes of the buffers driving the clock mesh. We show that such a sizing offers a better solution than inserting buffers of uniform size across the mesh. Due to the high redundancy, a mesh architecture offers high tolerance toward variations in clock skew. However, such a redundancy comes at the expense of mesh wire length and power dissipation. Based on survivable network theory, we formulate the problem to reduce the clock mesh by retaining only those edges that are critical to maintain redundancy. Such a formulation offers designer the option to tradeoff between power and tolerance to process variations. We present efficient postprocessing techniques to reduce the size of the mesh buffers after mesh reduction. Experimental results indicate that our techniques can result in power savings up to 28% with less than 3.3% delay penalty. We also present driver models that can help in simulating the clock mesh. Such models achieve near-HSPICE accuracy with significant speedup in run time.