AWESpice: a general tool for the accurate and efficient simulation of interconnect problems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
Driver modeling and alignment for worst-case delay noise
Proceedings of the 38th annual Design Automation Conference
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 42nd annual Design Automation Conference
CGTA: current gain-based timing analysis for logic cells
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Cell delay analysis based on rate-of-current change
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A multi-port current source model for multiple-input switching effects in CMOS library cells
Proceedings of the 43rd annual Design Automation Conference
Statistical logic cell delay analysis using a current-based model
Proceedings of the 43rd annual Design Automation Conference
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
WAVSTAN: waveform based variational static timing analysis
Proceedings of the conference on Design, automation and test in Europe
Accurate waveform modeling using singular value decomposition with applications to timing analysis
Proceedings of the 44th annual Design Automation Conference
Top-k aggressors sets in delay noise analysis
Proceedings of the 44th annual Design Automation Conference
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A robust finite-point based gate model considering process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Victim alignment in crosstalk aware timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A methodology for timing model characterization for statistical static timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Driver waveform computation for timing analysis with multiple voltage threshold driver models
Proceedings of the 45th annual Design Automation Conference
Towards a more physical approach to gate modeling for timing, noise, and power
Proceedings of the 45th annual Design Automation Conference
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
Challenges in gate level modeling for delay and SI at 65nm and below
Proceedings of the 45th annual Design Automation Conference
Addressing library creation challenges from recent Liberty extensions
Proceedings of the 45th annual Design Automation Conference
A current source model for CMOS logic cells considering multiple input switching and stack effect
Proceedings of the conference on Design, automation and test in Europe
Current source based standard cell model for accurate signal integrity and timing analysis
Proceedings of the conference on Design, automation and test in Europe
Worst-case aggressor-victim alignment with current-source driver models
Proceedings of the 46th Annual Design Automation Conference
Victim alignment in crosstalk-aware timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinatorial algorithms for fast clock mesh optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Current source modeling in the presence of body bias
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
FA-STAC: An algorithmic framework for fast and accurate coupling aware static timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compact current source models for timing analysis under temperature and body bias variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In This work we present a robust and efficient methodology for crosstalk-induced delay change analysis for ASIC design styles. The approach employs optimization methods to search for worst aggressor alignment, and it computes crosstalk induced delay change on each stage considering an impact on downstream logic. Computational efficiency is achieved using pre-characterized current models for drivers and compact macromodels for interconnect. The proposed methodology has been implemented in a commercial noise analysis tool. Experimental results obtained on industrial designs demonstrate high accuracy and reduced pessimism of the proposed methodology.