An effective capacitance based driver output model for on-chip RLC interconnects
Proceedings of the 40th annual Design Automation Conference
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
An Effective Current Source Cell Model for VDSM Delay Calculation
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Sensitivity-Based Gate Delay Propagation in Static Timing Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Equivalent waveform propagation for static timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A cell delay model based on rate-of-current-change is presented, which accounts for the impact of the shape of the noisy waveform on the output voltage waveform. More precisely, a pre-characterized table of time derivatives of the output current as a function of input voltage and output load values is constructed. The data in this table, in combination with the Taylor series expansion of the output current, is utilized to progressively compute the output current waveform, which is then integrated to produce the output voltage waveform. Experimental results show the effectiveness and efficiency of this new delay model.