A realizable driving point model for on-chip interconnect with inductance
Proceedings of the 37th Annual Design Automation Conference
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Proceedings of the 2004 international symposium on Physical design
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Proceedings of the 14th ACM Great Lakes symposium on VLSI
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ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
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ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Proceedings of the conference on Design, automation and test in Europe
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This paper presents a new library compatible approach to gate-level timing characterization in the presence of RLC interconnect loads. We describe a two-ramp model based on transmission line theory that accurately predicts both the 50% delay and waveform shape (slew rate) at the driver output when inductive effects are significant. The approach does not rely on piecewise linear Thevenin voltage sources. It is compatible with existing library characterization methods and is computationally efficient. Results are compared with SPICE and demonstrate typical errors under 10% for both delay and slew rate.