A realizable driving point model for on-chip interconnect with inductance
Proceedings of the 37th Annual Design Automation Conference
An effective capacitance based driver output model for on-chip RLC interconnects
Proceedings of the 40th annual Design Automation Conference
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As the feature size is scaled down to 90 nm and below, fundamental modeling changes, such as the nonlinearity and higher frequencies of signals, require driver-load models to take into account propagation delay and slew rates. The conventional single Ceff (one-ramp) with lumped RC model is no longer accurate. In this paper we propose a new multi-ramp model with general RLC interconnects as loads. This new model accurately predicts both the 50% delay and the overall output waveform shape with inductance effects.