IC analyses including extracted inductance models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-chip interconnections: impact of adjacent lines on timing
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Coping with buffer delay change due to power and ground noise
Proceedings of the 39th annual Design Automation Conference
Osculating Thevenin model for predicting delay and slew of capacitively characterized cells
Proceedings of the 39th annual Design Automation Conference
A library compatible driving point model for on-chip RLC interconnects
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Explicit gate delay model for timing evaluation
Proceedings of the 2003 international symposium on Physical design
A fast simulation approach for inductive effects of VLSI interconnects
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Shielding effect of on-chip interconnect inductance
Proceedings of the 13th ACM Great Lakes symposium on VLSI
An effective capacitance based driver output model for on-chip RLC interconnects
Proceedings of the 40th annual Design Automation Conference
Blade and razor: cell and interconnect delay analysis using current-based models
Proceedings of the 40th annual Design Automation Conference
Buffer delay change in the presence of power and ground noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A new multi-ramp driver model with RLC interconnect load
Proceedings of the 2004 international symposium on Physical design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Current Calculation on VLSI Signal Interconnects
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 42nd annual Design Automation Conference
IR Drop and Ground Bounce Awareness Timing Model
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A Waveform Independent Gate Model for Accurate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
General transistor-level methodology on VLSI low-power design
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load
Integration, the VLSI Journal
Interconnect modeling for improved system-level design optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Characterizing multistage nonlinear drivers and variability for accurate timing and noise analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Addressing library creation challenges from recent Liberty extensions
Proceedings of the 45th annual Design Automation Conference
Worst-case aggressor-victim alignment with current-source driver models
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Combinatorial algorithms for fast clock mesh optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate predictive interconnect modeling for system-level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Gate and cell level timing analysis remains popular yet inherently incompatible with RC and RCL interconnect loads. The Ceff concept was proposed in Qian et. al. (1994) to model the interaction of empirical gate/cell delay models and RC loads. The most efficient Ceff model works in terms of precharacterizing the parameters of a time varying Thevenin voltage source model (in series with a fixed resistor) over a wide range of effective capacitance load values. In this paper we generalize this Thevenin equivalent Ceff model to enable future technologies which may include reduced supply voltages and RCL loads, without further complicating the Ceff algorithm or iterations.