RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Improved Effective Capacitance Computations for Use in Logic and Layout Optimization
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Interconnect Delay and Slew Metrics Using the First Three Moments
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Calculating the effective capacitance for the RC interconnect in VDSM technologies
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
Interactive presentation: Process tolerant β-ratio modulation for ultra-dynamic voltage scaling
Proceedings of the conference on Design, automation and test in Europe
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A modeling technique for CMOS gates
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay analysis of CMOS gates using modified logical effort model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast interval-valued statistical modeling of interconnect and effective capacitance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel theory on parallel repeater-insertion methodologies for long on-chip interconnects
International Journal of Circuit Theory and Applications
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We propose an analytical closed-form gate-interconnect interdependent delay model that accounts for the dynamic behavior of signal slope across different regions of operation. In the presence of interconnects, the gate driver influences the input slope of the driven wire affecting the interconnect delay, and the driven wire acts as a parasitic load to the driver affecting the gate delay. Hence, it is essential to consider their interdependence for an accurate estimation of the circuit delay. The proposed model converts a signal slope into its effective fan-out for a simple yet accurate delay estimation. Simulations show that, for ISCAS benchmark circuits, our framework exhibits an error of Vdd = 1.2 V and 4.8% at Vdd = 0.3 V.