Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates

Authors:
Myeong-Eun Hwang;Seong-Ook Jung;Kaushik Roy
Affiliations:
Purdue Univ.;Yonsei Univ.;Purdue Univ.
Venue:
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Year:
2007

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Slope interconnect effort: gate-interconnect interdependent delay modeling for early CMOS circuit simulation

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Abstract

We present a circuit delay framework in a closed form that accounts for the dynamic behavior of signal slope in subthreshold (VDD VT) as well as superthreshold (VDD VT) regions. The proposed model converts a signal slope into its effective fanout for delay estimation. Simulations show that for ISCAS benchmark circuits, our framework exhibits a speedup of three orders of magnitude over HSPICE with 5% error. Measured results in 65nm show that for a wide range of interconnect lengths and geometries, the proposed model predicts the circuit delay with 5.7% error at the supply voltage of VDD = 1.2V , and with 4.5% error at VDD = 0.4V .