Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Fundamentals of computer-aided circuit simulation
Fundamentals of computer-aided circuit simulation
A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing metrics for physical design of deep submicron technologies
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Full-chip verification of UDSM designs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A floorplan-based planning methodology for power and clock distribution in ASICs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Aggressor alignment for worst-case coupling noise
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments
Proceedings of the 37th Annual Design Automation Conference
Interconnect parasitic extraction in the digital IC design methodology
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Static timing analysis taking crosstallk into account
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Predicting coupled noise in RC circuits
DATE '00 Proceedings of the conference on Design, automation and test in Europe
RC(L) interconnect sizing with second order considerations via posynomial programming
Proceedings of the 2001 international symposium on Physical design
On-chip interconnections: impact of adjacent lines on timing
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Timing analysis with crosstalk as fixpoints on complete lattice
Proceedings of the 38th annual Design Automation Conference
Driver modeling and alignment for worst-case delay noise
Proceedings of the 38th annual Design Automation Conference
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
Proceedings of the 38th annual Design Automation Conference
Osculating Thevenin model for predicting delay and slew of capacitively characterized cells
Proceedings of the 39th annual Design Automation Conference
Timed pattern generation for noise-on-delay calculation
Proceedings of the 39th annual Design Automation Conference
Silicon physical random functions
Proceedings of the 9th ACM conference on Computer and communications security
Efficient switching window computation for cross-talk noise
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Capturing crosstalk-induced waveform for accurate static timing analysis
Proceedings of the 2003 international symposium on Physical design
Explicit gate delay model for timing evaluation
Proceedings of the 2003 international symposium on Physical design
Minimum delay optimization for domino logic circuits---a coupling-aware approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Non-iterative switching window computation for delay-noise
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cross-Coupled Noise Propagation in VLSI Designs
Analog Integrated Circuits and Signal Processing
Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Method to Estimate Slew and Delay in Coupled Digital Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Delay Testing Considering Crosstalk-Induced Effects
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Worst Delay Estimation in Crosstalk Aware Static Timing Analysis
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
An Effective Current Source Cell Model for VDSM Delay Calculation
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
An Automated Shielding Algorithm and Tool For Dynamic Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Deep Sub-Micron Static Timing Analysis in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Efficient Delay Calculation in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Crosstalk Aware Static Timing Analysis: A Two Step Approach
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay-based circuit authentication and applications
Proceedings of the 2003 ACM symposium on Applied computing
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Reduction of coupling effects by optimizing the 3-D configuration of the routing grid
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Gate delay calculation considering the crosstalk capacitances
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A complete methodology for an accurate static noise analysis
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Statistical modeling of cross-coupling effects in VLSI interconnects
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A unified framework for statistical timing analysis with coupling and multiple input switching
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On bounding the delay of a critical path
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Efficient modeling techniques for dynamic voltage drop analysis
Proceedings of the 44th annual Design Automation Conference
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A "true" electrical cell model for timing, noise, and power grid verification
Proceedings of the 45th annual Design Automation Conference
Addressing library creation challenges from recent Liberty extensions
Proceedings of the 45th annual Design Automation Conference
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Crosstalk noise reduction in synthesized digital logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FA-STAC: An algorithmic framework for fast and accurate coupling aware static timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.01 |
In this paper we develop a gate level model that allows us to determinethe best and worst case delay when there is dominant interconnectcoupling. Assuming that the gate input windows oftransition are known, the model can predict the worst and bestcase noise, as well as the worst and best case impact on delay. Thisis done in terms of a Ceff based gate model under general RCinterconnect loading conditions.