Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Performance sensitivity analysis using statistical method and its applications to delay
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Improved Effective Capacitance Computations for Use in Logic and Layout Optimization
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Delay Testing Considering Power Supply Noise Effects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The increased noise/interference effects, such ascrosstalk, power supply noise, substrate noise anddistributed delay variations lead to increased signalintegrity problems in deep submicron designs. Theseproblems can cause logic errors and/or performancedegradation and need to be addressed both in the design for deep submicron and testing for deep submicron phase. Existing delay testing techniques cannotcapture the effects of noise on the cell/interconnectdelays. In his paper, we address the problem ofdelay testing considering crosstalk-induced delay effects. We propose solutions for target fault selection and pattern generation. The key elements ofour strategy are performance sensitivity analysis withrespect to crosstalk noise and a Genetic Algorithm(GA) based vector generation technique. The roleof performance sensitivity analysis is to consider theeffects of crosstalk noise during the target fault selection process. Next, for each selected fault consistingof a path and a set of crosstalk noise sources interacting with the path, we apply our iterative GA-basedpattern generation process. Our goal is to derive atest that produces large crosstalk-induced delay effect on the given path. Our technique allows considering any number of coupling sources along the targetpath. Due to its flexibility, efficiency and scalability,the technique can be applied to large circuits.