Statistical failure analysis of system timing
IBM Journal of Research and Development
A guide to simulation (2nd ed.)
A guide to simulation (2nd ed.)
Statistical delay modeling in logic design and synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
IEEE Transactions on Computers
New efficient algorithms for computing effective capacitance
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Enhancing test efficiency for delay fault testing using multiple-clocked schemes
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 40th annual Design Automation Conference
Delay Testing Considering Crosstalk-Induced Effects
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
On path-based learning and its applications in delay test and diagnosis
Proceedings of the 41st annual Design Automation Conference
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A path-based methodology for post-silicon timing validation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Experience in critical path selection for deep sub-micron delay test and timing validation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits
Journal of Electronic Testing: Theory and Applications
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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