Statistical delay modeling in logic design and synthesis

  • Authors:
  • Horng-Fei Jyu;Sharad Malik

  • Affiliations:
  • Department of Electrical Engineering, Princeton University, Princeton, NJ;Department of Electrical Engineering, Princeton University, Princeton, NJ

  • Venue:
  • DAC '94 Proceedings of the 31st annual Design Automation Conference
  • Year:
  • 1994

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Abstract