An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
High Speed VLSI Interconnections: Modeling, Analysis, and Simulation
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Process-Aggravated Noise (PAN): New Validation and Test Problems
Proceedings of the IEEE International Test Conference on Test and Design Validity
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Modeling and extraction of interconnect capacitances for multilayer VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Validation and test generation for oscillatory noise in VLSI interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
Proceedings of the 38th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Crosstalk fault detection by dynamic Idd
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results
Journal of Electronic Testing: Theory and Applications
TA-PSV—Timing Analysis for Partially Specified Vectors
Journal of Electronic Testing: Theory and Applications
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
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Minimum delay optimization for domino logic circuits---a coupling-aware approach
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ITC '00 Proceedings of the 2000 IEEE International Test Conference
Delay Testing Considering Crosstalk-Induced Effects
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Crosstalk Test Generation on Pseudo industrial Circuits: A Case Study
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
AC Scan Path Selection for Physical Debugging
IEEE Design & Test
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Pattern Selection for Testing of Deep Sub-Micron Timing Defects
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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Selection of Crosstalk-Induced Faults in Enhanced Delay Test
Journal of Electronic Testing: Theory and Applications
An empirical study of crosstalk in VDSM technologies
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
On bounding the delay of a critical path
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A new high-speed interconnect crosstalk fault model and compression for test space
WSEAS TRANSACTIONS on COMMUNICATIONS
A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits
Proceedings of the 19th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test pattern generation for crosstalk fault of high-speed interconnect
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
ATPG-XP: test generation form maximal crosstalk-induced faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
On ATPG for multiple aggressor crosstalk faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Electronic Testing: Theory and Applications
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits
International Journal of Computer Applications in Technology
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Due to technology scaling and increasing clockfrequency, problems due to noise effects lead to anincrease in design/debugging efforts and a decrease incircuit performance. This paper shows how crosstalkcoupling between lines can affect the propagation delayof signals in integrated circuits. A model is presented toevaluate the effect of parasitic coupling crosstalk.Conditions for the creation of the worst-case couplingand propagation of a delayed signal are presented. A testpattern generation algorithm utilizing the aboveconditions is presented and applied to several examplecircuits.