DAC '96 Proceedings of the 33rd annual Design Automation Conference
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th annual Design Automation Conference
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A new framework for static timing analysis, incremental timing refinement, and timing simulation
ATS '00 Proceedings of the 9th Asian Test Symposium
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A modeling technique for CMOS gates
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We propose a new concept-timing analysis for partially specified vectors (TA-PSV)-that enables the computation of tight timing windows. At one extreme, when the vectors are completely unspecified, TA-PSV reduces to static timing analysis (STA). At the other extreme, when the vectors are completely specified, TA-PSV performs timing simulation (TS). We present a systematic approach to construct a computationally feasible TA-PSV framework using a delay model that captures simultaneous to-controlling switching effects. We also demonstrate how TA-PSV can improve timing validation and also that TA-PSV significantly improves efficiency of timing-oriented test generation by reducing the search space.