Computer
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
Exclusive simulation of activity in digital networks
Communications of the ACM
Multi-Objective Optimization Using Evolutionary Algorithms
Multi-Objective Optimization Using Evolutionary Algorithms
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results
Journal of Electronic Testing: Theory and Applications
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Delay testing considering crosstalk-induced effects
Proceedings of the IEEE International Test Conference 2001
Fsimac: a fault simulator for asynchronous sequential circuits
ATS '00 Proceedings of the 9th Asian Test Symposium
Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Testing delay faults in asynchronous handshake circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits
Journal of Electronic Testing: Theory and Applications
International Journal of Computer Applications in Technology
ATPG-XP: test generation form maximal crosstalk-induced faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
Initialization-based test pattern generation for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A heuristic non-dominated sorting genetic algorithm-II for satellite-module layout optimisation
International Journal of Computer Applications in Technology
A heuristics method based on ant colony optimisation for redundancy allocation problems
International Journal of Computer Applications in Technology
Genetic algorithm based solution to dead-end problems in robot navigation
International Journal of Computer Applications in Technology
International Journal of Computer Applications in Technology
A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path Delay Test Generation Toward Activation of Worst Case Coupling Effects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-region particle swarm optimisation algorithm
International Journal of Computer Applications in Technology
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A new multi-objective genetic algorithm has been proposed for testing crosstalk delay faults in asynchronous sequential circuits that reduces average power dissipation during test application. The proposed Elitist Non-dominated Sorting Genetic Algorithm ENGA-based Automatic Test Pattern Generation ATPG for crosstalk induced delay faults generates test pattern set that has high fault coverage and low switching activity. Redundancy is introduced in ENGA-based ATPG by modifying the fault dropping phase and hence a very good reduction in transition activity is achieved. Tests are generated for several asynchronous SIS benchmark circuits. Experimental results demonstrate that ENGA gives higher fault coverage, reduced transitions and compact test vectors for most of the asynchronous benchmark circuits when compared with those generated by Weighted Sum Genetic Algorithm WSGA.