Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults

• Authors: Shweta Chary;Michael L. Bushnell
• Venue: VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
• Year: 2006

We present a new algorithm to generate path-delay fault tests for combined resistive vias, resistive bridges, and crosstalk capacitive coupling faults. We generate all possible coupling pairs in the circuit, and then we use the resistive bridging fault reduction algorithm to reduce these faults to the important ones. We use a simulation-based sequential automatic test-pattern generation (ATPG) system, with a multiple delay sequential fault simulator, to generate path-delay fault tests. We discuss the analog macromodels used to accurately model these fault effects elsewhere [1]. For defective resistive vias, we obtained a 71 to 93 % path-delay fault coverage on three combinational circuits and 49 to 71 % coverage on four sequential circuits. These are the first reported results for resistive via ATPG. We obtained resistive bridge path-delay fault coverages from 72 to 90 % on three combinational circuits and from 48 to 65 % on four sequential circuits.