STAX: statistical crosstalk target set compaction
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits
International Journal of Computer Applications in Technology
| Hi-index | 0.00 |
Today's high-performance chips are clocked at several GHz, resulting in designs whose performance specifications are violated by very small defects. High stuck-fault coverage is insufficient to detect these timing failures, so we propose a new analog coupling delay fault model and analog macromodeling technique to generate tests for these faults. To our knowledge, this is the first time that analog macromodeling, along with multiple-delay sequential digital fault simulation, using differing rise and fall times for digital logic gates, effectively detected coupling timing faults.We propose a new Crosstalk Candidate Reduction (CCR) algorithm, which looks at the entire set of possible signal line couplings and eliminates impossible and uninteresting couplings from the final list. On various circuits, CCR reduced the coupling candidates by 98.1%, on average. The analog macromodels eliminate errors and uncertainty about whether signals actually couple, and also avoid complete analog simulation during fault simulation, as all analog macromodels are precomputed. The analog macromodel is independent of the circuit-under-test, because it models generalized interconnect. The model efficiently handles large circuits with more than 10,000 coupling faults, while obtaining coupling fault coverages in the range of 4 to 10% on sequential circuits, and up to 33% on combinational circuits. These are the first coupling fault results for sequential circuits. Nearly all remaining coupling faults are redundant. We accurately eliminate many candidate coupling signals using an efficient time windowing technique that is of 0(# logic gates 脳 # fanouts) complexity.