ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Synchronous Test Generation Model for Asynchronous Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
Logically Determined Design: Clockless System Design with NULL Convention Logic
Logically Determined Design: Clockless System Design with NULL Convention Logic
Development of a large word-width high-speed asynchronous multiply and accumulate unit
Integration, the VLSI Journal
DFT techniques and automation for asynchronous NULL conventional logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partial-scan delay fault testing of asynchronous circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology
Journal of Electronic Testing: Theory and Applications
Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits
International Journal of Computer Applications in Technology
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Due to the absence of a global clock and the presence of more state holding elements that synchronize the control and data paths, conventional Automatic Test Pattern Generation (ATPG) algorithms fail when applied to asynchronous circuits, leading to poor fault coverage. This paper presents a design for test (DFT) technique for a popular asynchronous design paradigm called NULL Convention Logic (NCL) aimed at making NCL designs testable using existing DFT tools with reasonable gate overhead. The proposed technique performs test points (TPs) insertion using Sandia Controllability and Observability Program (SCOAP) analysis to enhance the controllability of feedback nets and observability for fault sites that are flagged unobservable. An Automatic DFT Insertion Flow (ADIF) algorithm and a custom ATPG NCL primitive gates library are developed. The developed DFT technique has been verified on several NCL benchmark circuits