Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Synchronous Test Generation Model for Asynchronous Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
Development of a large word-width high-speed asynchronous multiply and accumulate unit
Integration, the VLSI Journal
Partial-scan delay fault testing of asynchronous circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and characterization of convention self-timed multipliers
IEEE Design & Test
Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits
Journal of Electronic Testing: Theory and Applications
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology
Journal of Electronic Testing: Theory and Applications
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Conventional automatic test pattern generation (ATPG) algorithms fail when applied to asynchronous NULL Convention Logic (NCL) circuits due to the absence of a global clock and presence of more state-holding elements, leading to poor fault coverage. This paper presents a design-for-test (DFT) approach aimed at making asynchronous NCL designs testable using conventional ATPG programs. We propose an automatic DFT insertion flow (ADIF) methodology that performs scan and test point insertion on NCL designs to improve test coverage, using a custom ATPG library. Experimental results show significant increase in fault coverage for NCL cyclic and acyclic pipelined designs.