Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits
International Journal of Computer Applications in Technology
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VLSI circuits have become more susceptible to signal integrity related failures with the ever decreasing process geometries. Detection of crosstalk induced faults is thus important as capacitive crosstalk is one of the major sources of signal integrity related failures. Crosstalk glitch can result in erroneous output if the glitch effect propagates to a primary output or to an intermediate flip-flop. Similarly the crosstalk induced delay effects can also result in latching of an incorrect value if the delay exceeds the allowed margins. In this work a test generation and compaction method is proposed for crosstalk faults. Test patterns are generated by simultaneously considering the coupling capacitance, timing and functional incompatibilities between the victim and aggressor nets, to produce the practical maximum crosstalk noise. A unique method is proposed for finding the functional incompatibilities between interconnects. The generated test set is then compacted initially through pattern merging and then further through the fault-chaining algorithm. Three different implementations of this algorithm are compared on crosstalk test sets generated for ISCAS’85 benchmark circuits. Results show considerable reduction in crosstalk pessimism for the given layout and timing, as well as up to 75% reduction in overall test set size.