The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Testing delay-insensitive circuits
Testing delay-insensitive circuits
Automatic generation of synchronous test patterns for asynchronous circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Test Quality of Asynchronous Circuits: A Defect-oriented Evaluation
Proceedings of the IEEE International Test Conference on Test and Design Validity
Optimal Scan for Pipelined Testing: An Asynchronous Foundation
Proceedings of the IEEE International Test Conference on Test and Design Validity
High-level test evaluation of asynchronous circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Synchronous Test Generation Model for Asynchronous Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Automatic Scan Insertion and Test Generation for Asynchronous Circuits
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Multiplexor Based Test Method for Self-Timed Circuits
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partial-scan delay fault testing of asynchronous circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel automatic test pattern generator for asynchronous sequential digital circuits
Microelectronics Journal
Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits
International Journal of Computer Applications in Technology
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As a class of asynchronous circuits, handshake circuits are designed to tolerate variation of gate delays. However, certain timing constraints, such as the bundled data assumption, are exploited in the single-rail implementation of these circuits in order to simplify them. Therefore, any delay fault in the circuit may cause one of two problems, namely performance degradation or logic errors. To address the challenges incurred by the autonomous behavior of handshake circuits during at-speed test, we propose test methods for both types of delay faults based on a DFT strategy which greatly simplifies the complexity of test generation. The efficiency of the proposed methodology is demonstrated through experimental results on several handshake circuits.