A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Artificial intelligence: a modern approach
Artificial intelligence: a modern approach
Automatic generation of synchronous test patterns for asynchronous circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Critical hazard free test generation for asynchronous circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
ISMVL '01 Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic
Fast hazard detection in combinational circuits
Proceedings of the 41st annual Design Automation Conference
A Multiplexor Based Test Method for Self-Timed Circuits
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
SPIN-TEST: automatic test pattern generation for speed-independent circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Testing delay faults in asynchronous handshake circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Deductive Fault Simulation for Asynchronous Sequential Circuits
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Initialization-based test pattern generation for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
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A novel automatic test pattern generator (ATPG) for stuck-at faults of asynchronous sequential digital circuits is presented. The developed ATPG does not require support by any design-for-testability method nor external software tool. The shortest test sequence generation is guaranteed by breadth-first search. The contribution is unique hazard identification before the test generation process, state justification on the gate level, sequential fault propagation based on breadth-first search and stepwise composition of state graphs for sequential test generation. A new six-valued logic together with a new algorithm was developed for hazardous transition identification. The internal combinational ATPG allows to generate test patterns one by one and only if it is required by sequential test generation. The developed and implemented ATPG was tested with speed-independent and quasi-delay-insensitive benchmark circuits.