A Simulation-Based Method for Generating Tests for Sequential Circuits
IEEE Transactions on Computers
Testing delay-insensitive circuits
Testing delay-insensitive circuits
Artificial intelligence: a modern approach
Artificial intelligence: a modern approach
Automatic generation of synchronous test patterns for asynchronous circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Synchronous Test Generation Model for Asynchronous Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Fault simulation and random test generation for speed-independent circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
Partial-scan delay fault testing of asynchronous circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SPIN-PAC: test compaction for speed-independent circuits
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Initialization-based test pattern generation for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel automatic test pattern generator for asynchronous sequential digital circuits
Microelectronics Journal
Soft-error tolerance and mitigation in asynchronous burst-mode circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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SPIN-TEST is a simulation-based gate-level ATPG system for speed-independent circuits. Its core engine is an A* search algorithm which employs an accurate fault simulator and an efficient cost function to guide a deterministic test pattern generation phase. A random test pattern generation phase is also available in order to improve run time. The key ATPG challenge in speed-independent circuits is the generation of patterns that are valid independently of the relative timing and the order of arrival of signals. SPIN-TEST addresses this challenge by guaranteeing fault sensitization with hazard/race-free patterns and response observation that is not affected by oscillations or non-deterministic circuit states. Experimental results on benchmark circuits demonstrate the efficiency of SPIN-TEST in terms of both high fault coverage and low test generation time.