Randomized rounding: a technique for provably good algorithms and algorithmic proofs
Combinatorica - Theory of Computing
A Simulation-Based Method for Generating Tests for Sequential Circuits
IEEE Transactions on Computers
New Static Compaction Techniques of Test Sequences for Sequential Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Independent Test Sequence Compaction through Integer Programming
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Fault simulation and random test generation for speed-independent circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
SPIN-TEST: automatic test pattern generation for speed-independent circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
Accelerating the compaction of test sequences in sequential circuits through problem size reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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SPIN-PAC is a static test compaction method for Speed-Independent circuits. We demonstrate how the test sets can be compacted by combining multiple consecutive test vectors within a test sequence into a vector pair of higher Hamming distance, and by eliminating or pruning independent test sequences. We discuss the exponential nature of optimally solving this problem, we propose an efficient algorithm to approximate it, and we evaluate its performance through experiments.