New Static Compaction Techniques of Test Sequences for Sequential Circuits

Authors:
F. Corno;P. Prinetto;M. Rebaudengo;M. Sonza Reorda
Affiliations:
Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, Italy;Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, Italy;Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, Italy;Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, Italy
Venue:
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Year:
1997

Citing 6
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Abstract

This paper describes an algorithm for compacting the Test Sequences generated by an ATPG tool without reducing the number of faults they detect. The algorithm is based on re-ordering the sequences so that some of them can be shortened and some others eliminated. The problem is NP-complete, and we adopt Genetic Algorithms to obtain optimal solutions with acceptable computational requirements. As it requires just one preliminary Fault Simulation experiment, the approach is much more efficient than others proposed before; experimental results gathered with Test Sets generated by different ATPG tools show that the method is able to reduce the size of the Test Set by a factor varying between 50% and 62%.