Introduction to algorithms
Initializability Consideration in Sequential Machine Synthesis
IEEE Transactions on Computers
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Minimum length synchronizing sequences of finite state machine
DAC '93 Proceedings of the 30th international Design Automation Conference
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences
IEEE Transactions on Computers
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors
IEEE Transactions on Computers
A Hybrid Fault Simulator for Synchronous Sequential Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
On the Initialization of Sequential Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
New Static Compaction Techniques of Test Sequences for Sequential Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
MIX: A Test Generation System for Synchronous Sequential Circuits
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Initialization of sequential circuits and its application to ATPG
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On the (non-)resetability of synchronous sequential circuits
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Synchronization of large sequential circuits by partial reset
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
IEEE Transactions on Computers
Effective synchronizing algorithms
Expert Systems with Applications: An International Journal
Application of hierarchical classifier to minimal synchronizing word problem
ICAISC'12 Proceedings of the 11th international conference on Artificial Intelligence and Soft Computing - Volume Part I
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We consider two topics related to testing of synchronous sequential circuits. The first topic deals with synchronizable circuits and their synchronizing sequences. Synchronizing sequences are important in facilitating the test generation process for detectable faults, and in identifying undetectable faults. They are also important in determining whether an undetectable fault can be removed from a circuit without affecting its normal operation. We show a class of faults for which a synchronizing sequence for the faulty circuit can be easily determined from the synchronizing sequence of the fault free circuit. We also consider circuits that have a reset mechanism, and show how reset can ensure that no single fault would cause the circuit to become unsynchronizable. The second topic we consider deals with test sequence partitioning to speed up static test compaction. We propose a procedure for partitioning a given test sequence into subsequences such that the cumulative fault coverage of all the subsequences, when applied as independent test sequences, is equal to the fault coverage of the original sequence. Each subsequence can then be compacted independently.