Full scan fault coverage with partial scan
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Techniques for improving the efficiency of sequential circuit test generation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Design-for-testability for synchronous sequential circuits using locally available lines
Proceedings of the conference on Design, automation and test in Europe
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Deterministic test pattern generation techniques for sequential circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
8.2 On Synchronizing Sequences and Test Sequence Partitioning
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
8.3 On Removing Redundant Faults in Synchronous Sequential Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Application of Tools Developed at the University of Iowa to ITC-99 Benchmarks
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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We describe a test generation system for synchronous sequential circuits described at the gate level. The test generation system, called MIX, combines several test generation approaches to derive test sequences exhibiting very high fault coverages at relatively low CPU times. It is known that different faults in a synchronous sequential circuit may be more amenable to different test generation approaches. The strength of MIX stems from the fact that a large number of different approaches is used to attack faults with different characteristics. Several new techniques are incorporated into MIX, including a new definition of an XD-frontier, storing a partial state transition graph to help in the derivation of justification sequences, utilization of sequences generated for aborted faults, consideration of multiple time frames simultaneously during state justification, and dynamic computation of dependencies among flip-flops. A simplified form of test generation under the restricted multiple observation times test strategy is also employed, based on state expansion. Restricted multiple observation times fault simulation is used in MIX to identify detected faults beyond those detected by conventional fault simulation.