Introduction to algorithms
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Time-efficient automatic test pattern generation systems
Time-efficient automatic test pattern generation systems
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Simulation-based techniques for dynamic test sequence compaction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Automatic test generation using genetically-engineered distinguishing sequences
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Static compaction using overlapped restoration and segment pruning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Efficient Techniques for Dynamic Test Sequence Compaction
IEEE Transactions on Computers
An approach for improving the levels of compaction achieved by vector omission
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
A Practical Vector Restoration Technique for Large Sequential Circuits
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Sequence reordering to improve the levels of compaction achievable by static compaction procedures
Proceedings of the conference on Design, automation and test in Europe
State relaxation based subsequence removal for fast static compaction in sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Static test sequence compaction based on segment reordering and accelerated vector restoration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
8.2 On Synchronizing Sequences and Test Sequence Partitioning
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Putting the Squeeze on Test Sequences
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques
Proceedings of the conference on Design, automation and test in Europe - Volume 1
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Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states, and some states are frequently re-visited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and sufficient conditions are met for them. The techniques require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in significant compactions very quickly for circuits that have many revisited states.