Time-efficient automatic test pattern generation systems
Time-efficient automatic test pattern generation systems
Acceleration techniques for dynamic vector compaction
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Simulation-based techniques for dynamic test sequence compaction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Dynamic test compaction for synchronous sequential circuits using static compaction techniques
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Methods for Dynamic Test Vector compaction in Sequential Test Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Vector restoration based static compaction of test sequences for synchronous sequential circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Bottleneck removal algorithm for dynamic compaction in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Static compaction using overlapped restoration and segment pruning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proptest: a property based test pattern generator for sequential circuits using test compaction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An approach for improving the levels of compaction achieved by vector omission
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Sequence reordering to improve the levels of compaction achievable by static compaction procedures
Proceedings of the conference on Design, automation and test in Europe
ETW '00 Proceedings of the IEEE European Test Workshop
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Vector restoration based static compaction techniques [7]report significant compaction. In this paper we propose anew technique for static compaction which gives comparableor better compaction and runs 10 to 50 times fasterthan the fastest method proposed in [7]. The new techniquesolves the problem of compaction by dividing it intosmall subproblems (referred to as segments). The solutionsto these segments (or subproblems) are then dynamicallymerged providing excellent speed up without compromisingon compaction efficiency. Further speed up is achievedby compacting the individual segments using an acceleratedvector-restoration based compaction technique. If afault requires a sequence of length n to be detected, in ourapproach the number of vectors that need to be simulated forrestoring the sequence is O(n log2n), while the prevailingapproaches require simulation on O(n 2 ) vectors. Experimentalresults demonstrate substantial speedups comparedto the prevailing vector restoration based techniques, whilegiving comparable or better compaction. When comparedto the fastest method proposed in [7], our method was 5 to30 times faster on ISCAS circuits and 10 to 50 times fasteron real-life production circuits. For example, on one ofthe production circuits, our method gave 27 percent compactionin 188 seconds, while an improved version of thefastest method in [7] gave 25 percent compaction in 10200seconds. In addition, our method could successfully processlarge industrial designs which could not be completedby earlier techniques [7] in 2 CPU days.