Time-efficient automatic test pattern generation systems
Time-efficient automatic test pattern generation systems
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Simulation-based techniques for dynamic test sequence compaction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Static compaction using overlapped restoration and segment pruning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Efficient Techniques for Dynamic Test Sequence Compaction
IEEE Transactions on Computers
FreezeFrame: compact test generation using a frozen clock strategy
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A Practical Vector Restoration Technique for Large Sequential Circuits
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Static test sequence compaction based on segment reordering and accelerated vector restoration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
New Static Compaction Techniques of Test Sequences for Sequential Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Putting the Squeeze on Test Sequences
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A DFT Approach for Testing Embedded Systems Using DC Sensors
IEEE Design & Test
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Short test sequences for synchronous sequential circuits are important in reducing test application time and memory requirements. In addition, dynamic test compaction, where heuristics to generate short test sequences are incorporated into the test generation process, may also reduce test generation time. This is due to the fact that a smaller number of test vectors needs to be generated. We present a dynamic test compaction procedure. The compaction heuristics we use are based on previously proposed static compaction techniques. Conventionally, static compaction is applied as a postprocessing step, after the test sequence has been generated. In the proposed procedure, static compaction techniques are used while the test sequence is being generated, to reduce the need for postprocessing, or static compaction. Compared to other dynamic compaction procedures that generate very short test sequences, the computational overhead involved in the proposed procedure is significantly lower, yet short test sequences are obtained. The proposed techniques can be incorporated into other test generation procedures, to reduce the test lengths they produce.