A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
RF microelectronics
Optimal Zero-Aliasing Space Compaction of Test Responses
IEEE Transactions on Computers
Defect-oriented test scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic test compaction for synchronous sequential circuits using static compaction techniques
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
IEEE Transactions on Computers
BiST Model for IC RF-Transceiver Front-End
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
RF-BIST: Loopback Spectral Signature Analysis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Use of Embedded Sensors for Built-In-Test of RF Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
A low-cost test solution for wireless phone RFICs
IEEE Communications Magazine
Prediction of analog performance parameters using fast transient testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On proving the efficiency of alternative RF tests
Proceedings of the International Conference on Computer-Aided Design
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Today's consumer electronics must be portable, reliable at various operating environments, and power efficient. Thus, semiconductor manufacturers constantly upgrade their production technologies and incorporate intelligent circuit design techniques. With widespread advances in system integration techniques, manufacturers can bundle multiple functionalities onto a single chip, reducing the end product's form factor. However, with higher levels of integration and reduced pin count, test issues are becoming more critical. During high-volume production, variations in process parameters cause devices to vary significantly from their performance metrics, and test engineers have only limited test resources to perform at-speed testing. Generating diagnosis information is also challenging during product ramp-up, as very little information is available from the output pins about the different modules' functionalities. DFT seems to be the only viable solution in such a scenario. DFT can address various issues related to at-speed testing and high-speed test response capture by performing signal conditioning to more easily capture information at lower speeds. The authors present a method that uses embedded DC sensors at test observation nodes to simplify data capture and enhance test quality while performing at-speed tests during production testing. Experiments show that monitoring sensor outputs provides a very good estimate of complex, system-level specifications.