An improved RF loopback for test time reduction
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Testing Techniques for RF Wireless Transceivers
IEEE Design & Test
A DFT Approach for Testing Embedded Systems Using DC Sensors
IEEE Design & Test
Reducing Test Time Using an Enhanced RF Loopback
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Low-cost characterization and calibration of RF integrated circuits through I-Q data analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault Coverage Analysis of Peak-Detector Based BIST for RF LNAs
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
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Testing of on-chip RF and microwave circuits has always been a challenge to test engineers and has been more so in the recent past due to the high signal frequencies involved and the dense levels of circuit integration. In this paper, we propose to embed low-cost sensors into RF signal paths for the purpose of built-in test. The sensor characteristics are chosen in such a way that the sensor outputs, which are low frequency or DC signals, are tightly correlated with the target test specification values of the RF device-under-test. Hence, instead of testing the devices specifically for complex performance metrics (this is difficult for embedded circuits), the outputs of the sensors are used to accurately estimate the target test specification values when the device-under-test is stimulated with sinusoidal stimulus. This significantly impacts the cost of manufacturing test and allows testing to be performed using low-cost external testers. Using this method, the target test specification values can be estimated with an accuracy of +5% of their actual value.