Boundary Scan for 5-GHz RF Pins Using LC Isolation Networks
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A DFT Approach for Testing Embedded Systems Using DC Sensors
IEEE Design & Test
Towards Fault-Tolerant RF Front Ends
Journal of Electronic Testing: Theory and Applications
Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry
Proceedings of the conference on Design, automation and test in Europe
Practices in Mixed-Signal and RF IC Testing
IEEE Design & Test
Go/No-Go testing of VCO modulation RF transceivers through the delayed-RF setup
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Estimation of RF PA Nonlinearities after Cross-correlating Current and Output Voltage
Journal of Electronic Testing: Theory and Applications
DSP-driven self-tuning of RF circuits for process-induced performance variability
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low cost MIMO testing for RF integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures
Journal of Electronic Testing: Theory and Applications
On proving the efficiency of alternative RF tests
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.25 |
This article describes an IBM approach for testing high-volume, complex RFICs at a fraction of the cost of the integrated circuit. This approach uses a personal computer, a fast benchtop dc parametric analyzer, and RF-to-analog circuits to test an RFIC during the manufacturing process. The described system and methodology are specifically designed for high-volume test, where test cost is extremely important; they are not recommended for lower-volume products (less than 1 million per month). This article describes the system architecture and discusses design, maintenance, and implementation considerations. The system is designed to reduce the cost of a complex RFIC manufacturing test to equal that of a discrete component, such as a resistor or capacitor. Given the relatively easy implementation and the drastic cost reduction associated with the test solution, this architecture establishes a new standard for the future of RF test. In fact, this architecture may result in the fastest RF tester currently available.