Towards Fault-Tolerant RF Front Ends

Authors:
Tejasvi Das;Anand Gopalan;Clyde Washburn;P. R. Mukund
Affiliations:
Department of Electrical Engineering, Rochester Institute of Technology, Rochester, USA 14623;Department of Electrical Engineering, Rochester Institute of Technology, Rochester, USA 14623;Department of Electrical Engineering, Rochester Institute of Technology, Rochester, USA 14623;Department of Electrical Engineering, Rochester Institute of Technology, Rochester, USA 14623
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2006

Citing 4
Cited 1

End-to-End Test Strategy for Wireless Systems

Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A Current Sensor for On-Chip, Non-Intrusive Testing of RF Systems

VLSID '04 Proceedings of the 17th International Conference on VLSI Design
An architecture for self-test of a wireless communication system using sampled IQ modulation and boundary scan

IEEE Communications Magazine
A low-cost test solution for wireless phone RFICs

IEEE Communications Magazine

Test strategies for low power devices

Proceedings of the conference on Design, automation and test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

The continuing trends of scaling have brought with them an ever-increasing array of process faults and fabrication complexities. The relentless march towards miniaturization and massive integration, in addition to increasing operating frequencies has resulted in increasing concerns about the reliability of integrated RF front-ends. Coupled with rising cost per chip, the fault-tolerant paradigm has become pertinent in the RFIC domain. Due to the high frequencies involved, traditional fault-tolerance methods used in digital and lower frequency analog circuits cannot be applied. We propose a unique methodology to achieve fault-tolerance in RF circuits through dynamic sensing and on-chip self-correction, along with the development of robust algorithms. This technique, which poses minimal overheads and is transparent during `normal' use of the circuit, is demonstrated on a cascode LNA, since the LNA is critical for the performance of the entire front-end. We present simulation and fabricated results of the system designed in IBM 0.25 驴m CMOS 6RF process.