RF microelectronics
Proceedings of the 39th annual Design Automation Conference
Digital Image Processing
End-to-End Test Strategy for Wireless Systems
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Moving from mixed signal to RF test hardware development
Proceedings of the IEEE International Test Conference 2001
Testability implications in low-cost integrated radio transceivers: a Bluetooth case study
Proceedings of the IEEE International Test Conference 2001
A phase noise spectrum test solution for high volume mixed signal/wireless automatic test equipments
Proceedings of the IEEE International Test Conference 2001
Eigen-Signatures for Regularity-based IDDQ Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Wafer-level RF Test and DfT for VCO Modulating Transceiver Architecures
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
System-level Testing of RF Transmitter Specifications Using Optimized Periodic Bitstreams
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
RF-BIST: Loopback Spectral Signature Analysis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Mixed Loopback BiST for RF Digital Transceivers
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback Mode
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Seamless Test of Digital Components in Mixed-Signal Paths
IEEE Design & Test
IEEE Communications Magazine
A low-cost test solution for wireless phone RFICs
IEEE Communications Magazine
| Hi-index | 0.00 |
The increasing share of test and packaging as a percentage of the overall cost for RF transceivers necessitate, radically test new approaches to both wafer-level and final production testing. We present a new system-level test setup for voltage-controlled oscillator (VCO) modulating transceiver architectures that we call the delayed-RF setup, along with a novel, all-digital design-for-testability (DFT) modification that enables coverage of the most important system-level specifications. The delayed-RF setup can be used during wafer sort, thus preventing the packaging of nonfunctional dies. Based on this setup and the DFT technique, we present an automatic test development methodology for FM transceivers using frequency-domain signature analysis. We develop two distinct pass/fail criteria based on eigensignatures and envelope signatures and a test generation algorithm that aims at minimizing the required delay while attaining full coverage of target faults. We develop a fault injection and simulation platform for a VCO-modulation, low-IF transceiver architecture using MATLAB and behavioral models including nonideal response. The proposed methodology enables the automation of the test generation process, thus reduces the test development time. Experimental results have shown a 90% reduction in the required delay thereby reducing the cost of this test hardware item.