Discrete-time signal processing
Discrete-time signal processing
Proceedings of the 40th annual Design Automation Conference
Monte Carlo-Alternative Probabilistic Simulations for Analog Systems
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A CPPLL hierarchical optimization methodology considering jitter, power and locking time
Proceedings of the 43rd annual Design Automation Conference
Modeling and Simulation of ΔΣ Fractional-N PLL Frequency Synthesizer in Verilog-AMS
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Go/No-Go testing of VCO modulation RF transceivers through the delayed-RF setup
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and design of voltage-controlled oscillator based analog-to-digital converter
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Spur-free MASH delta-sigma modulation
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE custom integrated circuits conference
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Techniques for fast and accurate simulation of fractional-N synthesizers at a detailed behavioral level are presented. The techniques allow a uniform time step to be used for the simulator, and can be applied to a variety of phase locked loop (PLL) and delay locked loop (DLL) circuits beyond fractional-N synthesizers, as well as to a variety of simulation frameworks such as Verilog and Matlab. Simulated results from a custom C++ simulator are shown to compare well to measured results from a prototype fractional-N synthesizer using a &Sgr; modulator to dither its divide value.