Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm

Authors:
Charlotte Y. Lau;Michael H. Perrott
Affiliations:
Microsystems Technology Laboratory, MIT;Microsystems Technology Laboratory, MIT
Venue:
Proceedings of the 40th annual Design Automation Conference
Year:
2003

Citing 1
Cited 1

Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits

Proceedings of the 39th annual Design Automation Conference

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Analog Integrated Circuits and Signal Processing

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Abstract

A new methodology for designing fractional-N frequency synthesizers and other phase locked loop (PLL) circuits is presented. The approach achieves direct realization of the desired closed loop PLL transfer function given a set of user-specified parameters and automatically calculates the corresponding open loop PLL parameters. The algorithm also accomodates nonidealities such as parasitic poles and zeros. The entire methodology has been implemented in a GUI-based software package, which is used to verify the approach through comparison of the calculated and simulated dynamic and noise performance of a third order fractional-N frequency synthesizer.