Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits

Authors:
Michael H. Perrott
Affiliations:
-
Venue:
IEEE Design & Test
Year:
2002

Citing 2
Cited 1

Discrete-time signal processing

Discrete-time signal processing
Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits

Proceedings of the 39th annual Design Automation Conference

Multiple synchronous states in static delay-free mutually connected PLL networks

Signal Processing

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Abstract

Two techniques are presented that allow fast and accurate simulation of fractional-N synthesizers. A uniform time step allows implementation of these techniques in various simulationframeworks, such as Verilog, Matlab, and C or C++ programs. The techniques are also applicable to the simulation of other PLL systems, such as clock and data recovery circuits.Fractional-N Frequency Synthersizers provide high-speed frequency sources that can be accurately set with very high resolution--avaluable feature or many communication systems.