Distributed Synchronous Clocking
IEEE Transactions on Parallel and Distributed Systems
A Multi-PLL Clock Distribution Architecture for Gigascale Integration
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Recognition of noisy images by PLL networks
Signal Processing
IEEE Transactions on Signal Processing - Part I
A historical perspective on telecommunications network synchronization
IEEE Communications Magazine
Synchronization in digital system design
IEEE Journal on Selected Areas in Communications
A scalable synchronization protocol for large scale sensor networks and its applications
IEEE Journal on Selected Areas in Communications
Pattern recognition via synchronization in phase-locked loop neural networks
IEEE Transactions on Neural Networks
Computing with phase locked loops: choosing gains and delays
IEEE Transactions on Neural Networks
Time synchronization in sensor networks: a survey
IEEE Network: The Magazine of Global Internetworking
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In many engineering applications, the time coordination of geographically separated events is of fundamental importance, as in digital telecommunications and integrated digital circuits. Mutually connected (MC) networks are very good candidates for some new types of application, such as wireless sensor networks. This paper presents a study on the behavior of MC networks of digital phase-locked loops (DPLLs). Analytical results are derived showing that, even for static networks without delays, different synchronous states may exist for the network. An upper bound for the number of such states is also presented. Numerical simulations are used to show the following results: (i) the synchronization precision in MC DPLLs networks; (ii) the existence of synchronous states for the network does not guarantee its achievement and (iii) different synchronous states may be achieved for different initial conditions. These results are important in the neural computation context, as in this case, each synchronous state may be associated to a different analog memory information.