Ensuring Fault Tolerance of Phase-Locked Clocks
IEEE Transactions on Computers
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Transmission Delays in Hardware Clock Synchronization
IEEE Transactions on Computers
A communication architecture for multiprocessor networks
A communication architecture for multiprocessor networks
The NuMesh: a modular, scalable communications substrate
ICS '93 Proceedings of the 7th international conference on Supercomputing
Distributed synchronous clocking
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optical Switching and Networking
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It has historically been difficult to distribute a well-aligned hardware clock throughout the physical extent of a synchronous processor. Traditionally, this task has been accomplished by distributing the output of a central oscillator over a tree-like network, with repeaters at necessary intervals. While straightforward in concept, this method suffers from poor reliability, poor scalability and high skew. In this paper, we present an alternative approach驴Distributed Synchronous Clocking驴that maintains the simplicity of synchronous operation without suffering the drawbacks of centralized clocking. A network of independent oscillators takes the place of the centralized clock source, providing separate clock signals to the physically distant parts of a computing system. A distributed error correction algorithm effects global phase alignment by utilizing local comparisons of neighboring oscillator phase. In contrast to centralized clock distribution, distributed clocking has the inherent potential for complete scalability and graceful degradation. However, because oscillator phase is a modular quantity, a naive implementation of distributed synchronous clocking can suffer from mode-lock驴the trapping of local oscillator phase in undesirable stable equilibria where global phase is not aligned [26]. We present a simple method for eliminating this problem in $k$-ary Cartesian meshes and give a proof of its correctness for two-dimensional networks. An electronic implementation is also presented and several engineering issues relating to error tolerance are discussed.Index Terms驴Computer hardware clocking, clock synchronization, distributed clocking, oscillator synchronization, phase-locked loops, mode-locking.