Ensuring Fault Tolerance of Phase-Locked Clocks
IEEE Transactions on Computers
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Transmission Delays in Hardware Clock Synchronization
IEEE Transactions on Computers
Distributed Synchronous Clocking
IEEE Transactions on Parallel and Distributed Systems
A communication architecture for multiprocessor networks
A communication architecture for multiprocessor networks
Two Designs of a Fault-Tolerant Clocking System
IEEE Transactions on Computers
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
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It is difficult to distribute a well aligned hardware clock throughout the physical extent of a synchronous processor. In this paper, we present an alternative approach-Distributed Synchronous Clocking-that maintains the simplicity of synchronous operation without suffering the drawbacks of centralized clocking. A network of independent oscillators takes the place of the centralized clock source, providing separate clock signals to the physically distant parts of a computing system. A distributed error correction algorithm effects global phase alignment by utilizing local comparisons of neighboring oscillator phase. In contrast to centralized clock distribution, distributed synchronous clocking has the inherent potential for complete scalability and graceful degradation. However, because oscillator phase is a modular quantity, a naive implementation of distributed synchronous clocking can suffer from mode-lock-the trapping of local oscillator phase in undesirable stable equilibria where global phase is not aligned. We present a simple method for eliminating this problem in k-ary Cartesian meshes and show an electronic implementation with good performance.