An improved RF loopback for test time reduction
Proceedings of the conference on Design, automation and test in Europe: Proceedings
CMOS blocks for on-chip RF test
Analog Integrated Circuits and Signal Processing
Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique
Proceedings of the conference on Design, automation and test in Europe
Reducing Test Time Using an Enhanced RF Loopback
Journal of Electronic Testing: Theory and Applications
Go/No-Go testing of VCO modulation RF transceivers through the delayed-RF setup
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
A built-in-test circuit for RF differential low noise amplifiers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Built-in loopback test for IC RF transceivers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient EVM testing of wireless OFDM transceivers using null carriers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RF on-chip test by reconfiguration technique
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
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In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test patterngenerator and response analyzer. The test is oriented at spot defects in a transceiver front-end. Estimates for noise, signal power and nonlinear distortions such as EVM (or SER), gain and IP3, respectively, are considered the test responses. Limitations of these tests are investigated with respect to the test path properties, the strength of defects and circuit tolerances. The IP3 test complements the EVM (SER) and gain tests for some spot defects. The analysis is verified by simulation of a functional-level RF transceiver model implemented in Matlab驴.