BiST Model for IC RF-Transceiver Front-End
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A View from the Bottom: Nanometer Technology AC Parametric Failures " Why, Where, and How to Detect
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
RF-BIST: Loopback Spectral Signature Analysis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Mixed Loopback BiST for RF Digital Transceivers
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback Mode
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Low-cost Production Test of BER for Wireless Receivers
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Low-Cost Production Testing of Wireless Transmitters
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
CMOS blocks for on-chip RF test
Analog Integrated Circuits and Signal Processing
IEEE Communications Magazine
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The paper addresses on-chip test for IC RF transceivers. The baseband DSP available on chip serves as a tester while the RF front-end is reconfigured for test. The basic test setup is a loopback, enabled by a test attenuator and in some cases by an offset mixer, too. Different variants of this setup adopt the bypassing technique to boost testability. The existing limitations and tradeoffs in terms of test feasibility, controllability and observability versus the chip performance are discussed. The fault-oriented approach and the sensitization techniques are emphasized vs the functional test. The impact of production tolerances is addressed in terms of the detectability thresholds.