Low-cost testing of 5 GHz low noise amplifiers using new RF BIST circuit
Journal of Electronic Testing: Theory and Applications
A Novel RF Test Scheme Based on a DFT Method
Journal of Electronic Testing: Theory and Applications
A DFT Approach for Testing Embedded Systems Using DC Sensors
IEEE Design & Test
Electrical characterization of analogue and RF integrated circuits by thermal measurements
Microelectronics Journal
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Detailed characterization of transceiver parameters through loop-back-based BiST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Built-in loopback test for IC RF transceivers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RF on-chip test by reconfiguration technique
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
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In this paper a BiST technique for RF transceiver front-end is presented. The test is aimed atspot defects typical of mass production in CMOS process. The loop-back approach is used todetect the faults modeled as resistive breaks or bridges. The resulting impairments in gain, noise figure or selectivity of the RF blocks are considered functional-level faults, and as suchare subjected to test with PRBS stimulus and BER as the response at base-band. The extra test circuitry is limited and the on-chip resources are used to set-up the BiST. A model of GSMtransceiver with BiST is investigated to verify the proposed approach.