Built-in loopback test for IC RF transceivers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Delay Measurement Based Response Analysis for Timing Characterization
Journal of Electronic Testing: Theory and Applications
RF on-chip test by reconfiguration technique
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Flip-flop selection for partial enhanced scan to reduce transition test data volume
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Subtle failure mechanisms that arise from statistical distributions of the circuit parameters have been with us for many technology generations. However, since going from the 180 nm node to smaller nodes, the presence of these defects has increased to the point that they are nolonger considered an occasional nuisance. They are a primary worry since they are difficult todesign out with design rules, and they require special statistical and environmental settings toexpose failure. This paper will describe the origins of parametric failures (PFs), present data showing the magnitude of their variance, and discuss the conditions under which we can expect failures to occur or to be detected during the test process. Detection ischallenging, and PFs are a major source of field return. We expect PFs from intrinsic ICs (defect-free) and from extrinsic (defect) ICs. Resistive vias and metal cracks in general are a cause of PFs from ICs with parametric related defects. The detection of extrinsic PFs requires special care and astatistical analysis. This is a relatively new test paradigm [Seg03].