Sensing circuit for on-line detection of delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in timing parametric measurement unit
Proceedings of the IEEE International Test Conference 2001
BIST vs. ATE: need a different vehicle?
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Delay testing considering crosstalk-induced effects
Proceedings of the IEEE International Test Conference 2001
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Facilitating Rapid First Silicon Debug
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A View from the Bottom: Nanometer Technology AC Parametric Failures " Why, Where, and How to Detect
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
On-chip delay measurement for silicon debug
Proceedings of the 14th ACM Great Lakes symposium on VLSI
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Delay Fault Testing and Silicon Debug Using Scan Chains
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
On Hazard-free Patterns for Fine-delay Fault Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
A Scheme for On-Chip Timing Characterization
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
A novel framework for faster-than-at-speed delay test considering IR-drop effects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Circuit Failure Prediction and Its Application to Transistor Aging
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
An Experimental Delay Test Generator for LSI Logic
IEEE Transactions on Computers
Robust test generation for power supply noise induced path delay faults
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Small-delay defect detection in the presence of process variations
Microelectronics Journal
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
An All-Digital High-Precision Built-In Delay Time Measurement Circuit
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Multiple Coupling Effects Oriented Path Delay Test Generation
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Path-RO: a novel on-chip critical path delay measurement under process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Output Hazard-Free Transition Delay Fault Test Generation
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
A Low Overhead On-Chip Path Delay Measurement Circuit
ATS '09 Proceedings of the 2009 Asian Test Symposium
A unified online fault detection scheme via checking of stability violation
Proceedings of the Conference on Design, Automation and Test in Europe
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Timing Analysis: From Basic Principles to State of the Art
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Capturing post-silicon variation by layout-aware path-delay testing
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we present a novel on-chip path delay measurement architecture for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed on-chip path delay measurement (OCDM) circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed OCDM circuit can achieve a large delay measurement range with a small quantity of delay stages. A calibration circuit is incorporated into the proposed on-chip path delay measurement technique to calibrate the delay range of the delay stage under process variations. In addition, delay calibration for import lines is conducted to improve the precision of path delaymeasurement. Experimental results are presented to validate the proposed path delay measurement architecture.