Detecting Delay Flaws by Very-Low-Voltage Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testing for resistive opens and stuck opens
Proceedings of the IEEE International Test Conference 2001
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Timing Yield Estimation from Static Timing Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
MINVDD Testing for Weak CMOS ICs
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
On-chip delay measurement for silicon debug
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
On the effectiveness of detecting small delay defects in the slack interval
DBT '04 Proceedings of the 2004 IEEE International Workshop on Defect Based Testing
Small-Delay Defect Detection in the Presence of Process Variations
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
High-Quality Transition Fault ATPG for Small Delay Defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On identifying additive link metrics using linearly independent cycles and paths
IEEE/ACM Transactions on Networking (TON)
A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AC-plus scan methodology for small delay testing and characterization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Interconnect-based defects such as partial opens are becoming more prevalent in nanoscale designs. These are latent defects that affect circuit reliability and can be modeled as small-delay defects. Detecting such defects therefore requires faster than at-speed test clocks. In the paper we analyze the uncertainty introduced by process variations in detecting these defects. We propose new path selection algorithms that increase the probability of defect detection by taking into account the variability in path delays. Our results show that the new technique detects much smaller defects than the traditional approach of selecting the longest paths for test.