Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On Selecting Testable Paths in Scan Designs
Journal of Electronic Testing: Theory and Applications
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Delay Defect Screening using Process Monitor Structures
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study
ITC '04 Proceedings of the International Test Conference on International Test Conference
ALAPTF: A NEW TRANSITION FAULTMODEL AND THE ATPG ALGORITHM
ITC '04 Proceedings of the International Test Conference on International Test Conference
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Enhanced Timing-Based Transition Delay Testing for Small Delay Defects
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects
ATS '06 Proceedings of the 15th Asian Test Symposium
Automatic Generation of Instructions to Robustly Test Delay Defects in Processors
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Test Generation for Timing-Critical Transition Faults
ATS '07 Proceedings of the 16th Asian Test Symposium
Transition path delay faults: a new path delay fault model for small and large delay defects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Small-delay defect detection in the presence of process variations
Microelectronics Journal
Layout-aware scan chain reorder for launch-off-shift transition test coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Effective and Efficient Test Pattern Generation for Small Delay Defect
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Critical Path Selection for Delay Testing Considering Coupling Noise
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel test application scheme for high transition fault coverage and low test cost
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Statistical delay fault coverage and defect level for delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Classification and identification of nonrobust untestable path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Longest-path selection for delay test under process variation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Testing for small-delay defects (SDDs) requires fault-effect propagation along the longest testable paths. However, identification of the longest testable paths requires high CPU time, and the sensitization of all such paths leads to large pattern counts. Dynamic test compaction for small-delay defects is therefore necessary to reduce test-data volume. We present a new technique for identifying the longest testable paths through each gate in order to accelerate test generation for SDDs. The resulting test patterns sensitize the longest testable paths that pass through each SDD site. An efficient dynamic test compaction method based on structural analysis is presented to reduce the pattern count substantially, while ensuring that all the longest paths for each SDD are sensitized. Simulation results for a set of ISCAS 89 and IWLS 05 benchmark circuits demonstrate the effectiveness of this method.