Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Timing-aware ATPG [1] has been shown to be an effective method for generating high-quality test sets that detect small delay defects through the longest paths. However, this method usually results in a much higher test pattern count than the traditional transition fault test generation. In this paper, we propose a new criterion that identifies a subset of transition faults to be targeted by the timing-aware ATPG in order to reduce test pattern count while minimizing the impact on the overall delay test quality. The new criterion utilizes the minimal static slack to classify certain transition faults as timing-critical. The test pattern count reduction is achieved by restricting the timing-aware ATPG to targeting the timing-critical transition faults while using traditional transition fault test generation for the remaining transition faults. The experimental results for the industrial circuits show the effectiveness of the proposed method.