Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
A novel scan architecture for power-efficient, rapid test
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On Structural vs. Functional Testing for Delay Faults
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
On Achieving Complete Coverage of Delay Faults in Full Scan Circuits using Locally Available Lines
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Efficient techniques for transition testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Enhancing Delay Fault Coverage through Low Power Segmented Scan
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Enhanced Broadside Testing for Improved Transition Fault Coverage
ATS '07 Proceedings of the 16th Asian Test Symposium
Layout-aware scan chain reorder for launch-off-shift transition test coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Conflict driven scan chain configuration for high transition fault coverage and low test power
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Complete Functional Broadside Tests for Transition Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DTBR: A dynamic thermal-balance routing algorithm for Network-on-Chip
Computers and Electrical Engineering
SAT-based generation of compressed skewed-load tests for transition delay faults
Microprocessors & Microsystems
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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This paper presents a new method for improving transition fault coverage in hybrid scan testing. It is based on a novel test application scheme, in order to break the functional dependence of broadside testing. The new technique analyzes the automatic test pattern generation conflicts in broadside test generation and skewed-load test generation, and tries to control the flip-flops with the most influence on fault coverage. The conflict-driven selection method selects some flip-flops that work in the enhanced scan mode or skewed-load scan mode. And the conflict-driven reordering method distributes the selected flipflops into different chains. In the multiple scan chain architecture, to avoid too many scan-in pins, some chains are driven by the same scan-in pin to construct a tree-based architecture. Based on the architecture, the new test application scheme allows some flipflops to work in enhanced scan or skewed-load mode, while most of others to work in the traditional broadside scan mode. With the efficient conflict-driven selection and reordering schemes, fault coverage is improved greatly, which can also reduce test application time and test data volume. Experimental results show that fault coverage based on the proposed method is comparable that of enhanced scan.